module ram_selector (
    input wire clk,
    input wire rst_n,
    input wire we,
    input wire [7:0] ram0_burst_len,
    input wire [7:0] ram1_burst_len,
    input wire [7:0] ram2_burst_len,
    output reg [1:0] current_ram
);

    // 状态定义
    localparam RAM0_C = 2'b00;
    localparam RAM1_B = 2'b01;
    localparam RAM2_A = 2'b10;
    localparam IDLE   = 2'b11;

    // 内部信号
    reg [7:0] transfer_counter;
    reg [7:0] current_target;

    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            current_ram <= RAM0_C;
            transfer_counter <= 8'd0;
            current_target <= 8'd0;
        end
        else begin
            case (current_ram)
                RAM0_C: begin
                    current_target <= ram0_burst_len;
                    if (we) begin
                        if (transfer_counter == current_target - 1) begin
                            current_ram <= RAM1_B;
                            transfer_counter <= 8'd0;
                        end
                        else begin
                            transfer_counter <= transfer_counter + 1;
                        end
                    end
                end
                
                RAM1_B: begin
                    current_target <= ram1_burst_len;
                    if (we) begin
                        if (transfer_counter == current_target - 1) begin
                            current_ram <= RAM2_A;
                            transfer_counter <= 8'd0;
                        end
                        else begin
                            transfer_counter <= transfer_counter + 1;
                        end
                    end
                end
                
                RAM2_A: begin
                    current_target <= ram2_burst_len;
                    if (we) begin
                        if (transfer_counter == current_target - 1) begin
                            current_ram <= IDLE;
                            transfer_counter <= 8'd0;
                        end
                        else begin
                            transfer_counter <= transfer_counter + 1;
                        end
                    end
                end
                
                IDLE: begin
                    // 传输完成，保持空闲状态
                    current_target <= 8'd0;
                end
                
                default: begin
                    current_ram <= RAM0_C;
                    transfer_counter <= 8'd0;
                    current_target <= 8'd0;
                end
            endcase
        end
    end

endmodule 